1. Field of the Invention
The present invention relates generally to an analog-to-digital (A/D) converter, and more particularly to such an A/D converter referred to as deserializer system which divides data to be converted into upper data and lower data for carrying out A/D conversion.
2. Description of the Prior Art
There is generally known, as a high speed A/D converter, a parallel type (flash system) A/D converter which is provided with a comparator for each of all levels to be converted to process all the levels in parallel. However, the parallel type A/D converter requires not less than 255 comparators for A/D conversion of, for example, eight bits, and the resulting circuit configuration is extremely large.
On the other hand, U.S. Pat. No. 4,533,903, assigned to the same assignee of the present invention, proposes an A/D converter referred to as deserializer system which divides input data into upper data and lower data. According to this deserializer system, the number of comparators required for an eight-bit A/D conversion can be largely reduced to 15 for the upper data and 15 for the lower data, i.e., a total of 30.
However, since the A/D converter in accordance with the deserializer system performs A/D conversion twice, i.e. first a conversion for upper data and thereafter a conversion for lower data, it requires comparisons in two stages, thereby incurring a problem that the A/D conversion speed is decreased to approximately one-half.
Also, if a perfect matching is not provided between a circuit for A/D converting the upper data and that for the lower data, there is a fear that the linearity is deteriorated in the vicinity of the boundary of the upper data.
In the above-mentioned circuit, it is necessary to provide the same input signal upon A/D converting the upper data and the lower data. For this reason, various methods have been provided, such as a method of sampling and holding an input signal before supplying the same to the comparators for conversions of the upper and lower data.
However, it is impossible to eliminate fluctuations in signal voltage in a sample and hold circuit. Therefore, if a fluctuation causes a signal level to be increased, the signal level supplied for converting the lower data is higher than that for converting the upper data, whereby if the signal is converted in the vicinity of the boundary of conversion in the process of the upper data conversion, the signal supplied for the lower data conversion, thus having a higher level than the signal supplied for the upper data conversion, will exceed the upper limit of the conversion range of the lower data. In such occasion, the lower data remains a maximal value, thereby presenting distortion due to the width of fluctuation .DELTA.V caused by the sample and hold circuit.